Senior Digital Engineer
Core
Architect, design, and integrate low-power digital circuits for mixed-signal data conversion and power management products in advanced process nodes.
Role type
Senior IC digital design engineer (mixed-signal/power management)
Builds
Low-power digital circuits for mixed-signal data conversion and power management products
Domain
Semiconductor / ASIC design / Power management
Deliverable
production ML models | product features
Required skills
Digital RTL design (Verilog/SystemVerilog), ASIC design methodology, Mixed-signal design flow, Timing analysis and closure, DFT strategy, RTL and gate-level debugging, Block and chip-level verification, P&R interaction, UPF (power gating)
Preferred skills
Mixed-signal design methodologies, Design constraints and hand-off to P&R, Static Timing Analysis (STA), Low-power design techniques, Power analysis and optimization, UVM, AMBA or I2C protocols
Technologies
Verilog, SystemVerilog, UVM, AMBA, I2C, UPF, Lint, CDC, RDC, STA
Responsibilities
Interpret high-level requirements to architect and design digital circuits; Support full product lifecycle from concept to mass-production; Design digital RTL meeting timing, area, and power specs; Integrate designs and run simulations; Participate in mixed-signal design flow (synthesis, timing analysis, CDC, RDC); Collaborate with P&R team for layout generation; Support DFT and test-case development; Perform silicon evaluation and document errata.
Seniority
Senior, hands-on IC
