Senior IP Design Engineer
Core
Designing reconfigurable Fuse and JTAG Subsystems and RTL for complex SoCs across Enterprise, Auto, and Client markets.
Role type
Senior IC digital hardware design engineer
Builds
Reconfigurable IP features and SoC subsystems for Arm's hardware
Domain
Semiconductor / SoC design
Deliverable
production ML models | product features | infrastructure
Required skills
System Verilog, RTL design, static design checks (linting, CDC/RDC, X-propagation), SoC design, reconfigurable IP design
Preferred skills
ARM-based designs, OTP/Fuse usage models, JTAG/TAP protocols, Perl/Python scripting, analog hard IP integration, power and clock domain crossing, DFT methodologies
Technologies
System Verilog, Perl, Python
Responsibilities
Develop IP features for reconfigurable Fuse and JTAG Subsystems; Develop RTL, fix bugs, perform design checks, and generate implementation constraints; Ensure designs meet quality, reliability, and manufacturing needs; Partner with verification to review test plans and debug issues; Act as 1-Arm to ensure best solutions are used.
Seniority
Senior, hands-on IC