Staff Engineer, Physical Design
Core
Drive physical design implementation, timing closure, and structural backbone for next-generation RISC-V processor designs, focusing on global signal planning and high-performance interconnects.
Role type
Staff Physical Design Engineer (IC)
Builds
High-performance silicon implementations of RISC-V compute platforms
Domain
Semiconductor / Chip Design / VLSI
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Advanced clock distribution architecture, global interconnect routing, RC delay modeling, transistor-level timing analysis, EDA tool mastery (Synopsys/Cadence), multi-corner multi-mode timing closure, tape-out experience on advanced nodes
Preferred skills
Experience with 7nm and below process nodes, deep understanding of CMOS circuit behavior, expertise in mesh/H-tree clock topologies
Technologies
Synopsys Fusion Compiler, Synopsys PrimeTime, Cadence Innovus, Cadence Tempus
Responsibilities
Architect high-speed low-skew clock distribution networks; manage physical implementation of global signal planning and high-speed bus routing; resolve deep-submicron physical effects like crosstalk and IR-drop; partner with RTL teams to optimize microarchitecture for PPA; mentor junior engineers on design methodologies
Seniority
Staff, hands-on IC with technical leadership