Senior Engineer-STA
Core
Developing and validating timing constraints and performing timing analysis/closure for System-on-Chip (SoC) and block/subsystem levels.
Role type
Senior IC physical implementation engineer (static timing analysis)
Builds
SoC and block-level silicon designs meeting timing constraints
Domain
Semiconductor / VLSI Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Static timing analysis (STA), ECO generation, IP integration, TCL/PERL/Python scripting, sub-7nm technology node experience, data analysis
Preferred skills
Experience with PrimeTime, Tempus, Tweaker tools, collaboration with silicon engineering groups
Technologies
PrimeTime, Tempus, Tweaker, TCL, PERL, Python
Responsibilities
Develop and validate timing constraints for functional and test modes; Perform timing analysis and closure at SoC and block levels; Generate and track ECOs to closure with partners
Seniority
Senior, hands-on IC