Senior STA Engineer
Core
Drive static timing analysis, timing closure, and signoff quality for complex ASIC and SoC designs at advanced process nodes.
Role type
Senior IC physical design and timing engineer
Builds
ASIC and SoC silicon implementations
Domain
Semiconductor / VLSI Design
Required skills
Static timing analysis, timing closure, EDA tools (PrimeTime, ICC2, Innovus, Tempus), Tcl scripting, setup/hold violation debugging, clocking analysis, ECO impact analysis, cross-functional collaboration
Preferred skills
Advanced-node implementation, MMMC flows, SI analysis, OCV/AOCV/POCV, power-aware timing analysis, timing methodology development, automation scripting (Perl/Python)
Technologies
PrimeTime, ICC2, Innovus, Tempus, Tcl, Perl, Python
Responsibilities
Drive static timing analysis and timing closure for block and/or full-chip designs; Develop, review, and debug timing constraints, scenarios, and signoff checks; Analyze setup, hold, noise, and variation-related timing issues; Partner with physical design engineers on floorplan, CTS, route, ECO, and convergence activities; Review reports, identify root causes of violations, and recommend high-quality fixes; Improve timing methodology, automation, and debug efficiency using scripting.
Seniority
Senior, hands-on IC
