ASIC Physical Design
1,421 open positions
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Application Engineer AlteraRemote 3d Senior Applications Engineer enabling customer success and design wins for Altera FPGA solutions through strategic technical guidance and complex problem resolution.
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Hardware Engineer CiscoSan Jose, California, US $155k–$155k3d Design and develop high-performance, secure firewall hardware platforms including FPGA-based crypto accelerators and network processing units for enterprise, data center, and cloud networks.
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Physical Design Engineer, Timing TenstorrentAustin $100k–$100k3d Converge multi-million-gate designs on advanced process nodes through static timing analysis (STA) and partner with cross-functional teams for final signoff and tapeout.
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Staff SoC Architect GraphcoreBristol 3d Define SoC architecture for next-generation AI acceleration platforms, specifying subsystems, interfaces, and interconnects to guide implementation and validation.
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Physical Design Intern AmbiqmicroincSingapore 3d Intern role supporting block-level physical implementation for ultra-low power System-on-Chip (SoC) designs in advanced process nodes.
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Silicon Digital IP / Subsystem Architect AsteralabsBengaluru 4d Define architecture and technical direction for complex semiconductor IPs and subsystems, owning the definition from requirements through implementation.
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Senior Board Design Hardware Engineer NVIDIAIsrael, Raanana 4d Lead complex switch system and board designs from concept through mass production for NVIDIA's next-generation data center networking infrastructure.
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Digital IP Design Engineer (f/m/d) NxpMunich 4d Develop and implement digital IP and logic designs for complex Mixed-Signal System-on-Chips (SoCs), including automotive microprocessors, application processors, and AI/ML cores.
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Staff Engineer, Design Verification Engineering AnalogdevicesIndia, Bangalore, RMZ 4d Architecting and designing key digital blocks in SoC designs, optimizing micro-architecture for power, performance, and area tradeoffs, and leading design verification activities.
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Senior Principal Digital IC Design Engineer MarvellSanta Clara, CA, US $182k–$273k4d Design, develop, implement, verify, and document micro-architecture and RTL for complex power management integrated circuits used in high-speed interconnects for hyperscaler data centers.
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Senior Staff Engineer, Physical Design Samsung Electronics3900 N Capital of Texas Hwy, Austin, TX, USA $180k–$180k4d Senior Staff GPU Physical Design Engineer shaping physical implementation and methodology innovation for high-performance GPU and system-level IP to achieve market-differentiating power, performance, and area (PPA) goals.
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STA & Synthesis Lead Engineer↗ SemidynamicsBarcelona, CT, ES 4d Lead engineer driving logic synthesis, static timing analysis (STA), and timing closure for complex digital designs from RTL to implementation, ensuring Power, Performance, and Area (PPA) targets are met.
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Senior Physical Design Engineer CienaOttawa, CA $109k–$109k4d Develop large mixed-signal SoC ASICs targeting advanced technology nodes to optimize performance, power efficiency, and area for Ciena's WaveLogic optical fiber transmission solutions.
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CPU–SoC Mask Layout Designer (Diploma Level Contract role) - Silicon Engineering Group (SiG) IntelMalaysia, Penang 4d Create mask layouts for next-generation SoC/CPU and perform design verification for process rules, reliability, and power integrity.
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Sr. Manager, Physical Design Engineering, Annapurna Labs
AmazonAustin, Texas, United States
$240k–$240k4d
Lead a world-class Physical Design team delivering multi-billion-transistor ML accelerator SoCs (Inferentia, Trainium) on advanced tech nodes.
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ASIC Digital Design, Staff Engineer↗ SynopsysPorto, P13, PT 4d Design and implement RTL for digital and mixed signal IP blocks, run synthesis exploration, and support DFT/ATPG flows to create semiconductor IP for automotive, mobile, data center, HPC, and AI applications.
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Staff / Senior Staff Physical Design Engineer (IC Backend)↗ Leadtop TechnologyClementi, S00, SG 4d Lead physical design tasks from netlist to GDSII, including floorplanning, P&R, verification, and tapeout for advanced process nodes.
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Digital/FPGA Engineer↗ Per Vices CorporationToronto, ON, CA 4d Design, simulate, implement, and validate FPGA-based architectures for Software Defined Radios (SDRs) interfacing high-speed data buses with converters.
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Senior Digital PD Engineer Texas InstrumentsBengaluru, Karnataka, India 4d Senior Digital Physical Design Engineer responsible for end-to-end RTL-to-GDSII implementation, timing closure, and PPA optimization for high-speed mixed-signal communication circuits.
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Senior Staff Product Development Engineering↗ AMDTampines, S00, SG 4d Technical lead specializing in FPGA, hardware programmable SoCs, and ACAP to deliver next-gen processor technology for Data Center, Automotive, and Communications markets.
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SoC RTL Design Engineer↗ Quadric Pty LtdCA $175k–$175k4d Design and integrate SoC subsystems for a General Purpose Neural Processing Unit (GPNPU) enabling neural network inference and C++ code on a single programmable architecture.
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Silicon Senior RTL Engineer, Google Cloud↗
GoogleKA, IN
4d
Design and verify custom silicon solutions (TPU) to accelerate AI/ML computation in Google's data centers.
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Silicon Engineer, Custom Circuits and SRAM, Google Cloud↗
GoogleKA, IN
4d
Design and integrate custom silicon circuits, SRAMs, and memories to power Google's TPU and AI/ML hardware acceleration.
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ASIC Principal Engineer HpeBengaluru, Karnātaka, India 4d Define and architect high-performance blocks for advanced networking ASICs, focusing on micro-architecture, logic design, timing analysis, and collaboration with verification and physical design teams.
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Lead Design Engineer CadenceGYEONGGI-DO (Seoul) 4d Lead physical design implementation for ASICs at advanced technology nodes, focusing on low power and high speed designs.
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Lead RTL Engineer ( Mixed-Signal IPs) SilabsHyderabad 4d Develop, integrate, and verify digital RTL blocks within mixed-signal subsystems (ADC/DAC, PLL/DLL, power management) for low-power wireless SoCs.
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Staff Board Design Engineer (PCB CAD) ConnectTW - Taipei City - Suite C7F 4d Translating system and architectural specifications into detailed design specs, schematics, and physical PCB layouts for server motherboards and add-in cards.
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Fabric IP Designer MicrosoftUnited States, North Carolina, Raleigh 4d Design advanced memory sub-system components and automation/AI solutions for complex coherent fabrics.
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Staff Digital Engineer Renesas-ElectronicsChandler, Arizona, us 4d Design complex Power Management IC (PMIC) chips for automotive applications, focusing on digital RTL design, integration, and mixed-signal design flow.
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Senior ASIC Digital Lead - ATPG & Methodology (f/m/div.) Bosch-GroupReutlingen, BW, de $88k–$88k4d Senior technical lead responsible for digital ASIC design scope, DFT/ATPG integration, and test flow stability across complex mobility system projects.
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Physical Design Engineer↗ QualcommMarkham, ON, CA $108k–$108k5d Execute physical design flow from synthesized netlist to tape-out for complex, high-speed, and low-power ASICs and SoCs.
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Digital ASIC SoC Architect, Stockholm AxisSweden - Stockholm 5d Define system-level requirements and architecture for ARTPEC SoC chips used in surveillance cameras, selecting third-party IPs and supporting RTL design/verification teams.
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