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Hardware & Physical Engineering
› ASIC Physical Design
ASIC Physical Design
2,710 open positions
MTS Silicon Design Engineer
Advanced Micro Devices, Inc
Boxborough, Massachusetts
4d
Research, design, develop, and test electronic components and systems for semiconductor manufacturing, specifically overseeing ASIC development, architecture design, logic design, and system simulation for complex integrated circuits.
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MTS Silicon Design Engineer
Advanced Micro Devices, Inc
San Jose, California
4d
Research, design, develop, and test electronic components and systems for semiconductor manufacturing, overseeing ASIC development from architecture to layout.
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Silicon Design Engineer
Advanced Micro Devices, Inc
Austin, Texas
4d
Research, design, develop, and test electronic components and systems for semiconductor and related device manufacturing, employing knowledge of electronic theory.
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Sr. Silicon Design Engineer
Advanced Micro Devices, Inc
Austin, Texas
4d
Research, design, develop, and test electronic components and systems for semiconductor and related device manufacturing, focusing on ASIC development.
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Sr. Silicon Design Engineer
Advanced Micro Devices, Inc
Remote
4d
Research, design, develop, and test electronic components and systems for semiconductor and related device manufacturing, specifically focusing on ASIC development and complex integrated circuit layout.
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Sr. Silicon Design Engineer
Advanced Micro Devices, Inc
Fort Collins, Colorado
4d
Research, design, develop, and test electronic components and systems for semiconductor and related device manufacturing, specifically focusing on ASIC development and complex integrated circuit layout.
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Hardware Engineer
ARK Solutions, Inc.
USA
$62k–$102k
4d
Lead FPGA development and design in embedded architectures that interface with software modules for complex space-related problems.
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Lead FPGA System Design Engineer
Advanced Micro Devices, Inc
Hyderabad, India
4d
Lead FPGA System Design Engineer driving hardware system design, RTL coding, simulation, and deep learning algorithm research for AMD UltraScale+ MPSoC and Versal solutions.
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FY27 Intern - Digital Design Engineering Intern - Canada (16 months)
Qualcomm
Toronto, Ontario, Canada
4d
Intern role focused on Digital Design Engineering, specifically RTL coding, DFT integration, and verification for custom SoCs and IPs.
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System Application Engineer
NVIDIA
Taiwan, Taipei
4d
Develop and implement NVIDIA products with SOC design, providing technical support during development, testing, and production for partners.
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Power Engineer- Cisco Silicon One
Cisco
Caesarea, Israel
4d
Lead the architecture, design, and optimization of high-density power delivery architectures and complex power systems for next-generation networking platforms and Silicon One ASICs.
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Hardware Engineer- Cisco Silicon One
Cisco
Caesarea, Israel
4d
Architect innovative hardware platforms and high-performance board designs for Cisco's core Switching, Routing, and Wireless products.
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Senior ASIC Engineer
NVIDIA
China, Shanghai
4d
Develop advanced video IP for SoCs and GPUs, covering algorithm and architecture exploration through implementation and verification.
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System Application Engineer
NVIDIA
Taiwan, Taipei
4d
Develop and implement NVIDIA products with SOC design, providing technical support during development, testing, and production while driving partner design reviews.
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Senior ASIC Engineer
NVIDIA
China, Shanghai
4d
Design advanced video IP for SoCs and GPUs, covering algorithm exploration, microarchitecture definition, and RTL implementation.
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Senior CPU Architect
NVIDIA
China, Shanghai
4d
Architecting world-class RISC-V based micro-processors for NVIDIA GPU and Tegra SOC.
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SoC Systems Performance Engineer, Senior
Qualcomm
San Diego, California, United States of America
$130k–$194k
4d
Lead performance and systems studies for next-generation SoC products, defining architecture plans balancing performance, power, and thermal while collaborating with HW/SW teams.
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Senior ASIC Board Design- Cisco Silicon One
Cisco
Caesarea, Israel
4d
Spearhead innovative silicon architecture for AI infrastructure, guiding board design from concept through to mass production for Cisco's core Switching, Routing, and Wireless products.
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Senior CPU Architect
NVIDIA
China, Shanghai
4d
Architecting world-class RISC-V based embedded micro-processors for NVIDIA GPU and Tegra SOC.
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Physical Design Engineer
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Trulyyy
Singapore, S00, SG
4d
Lead end-to-end digital backend execution (netlist to GDSII) and drive full-chip static timing analysis for high-end IC components.
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ASIC Board Design Engineer — Cisco Silicon One
Cisco
Caesarea, Israel
4d
Architect high-performance hardware platforms and lead complex board designs from concept to mass production for Cisco's core Switching, Routing, and Wireless products.
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PCB Layout Engineer- Cisco Silicon One
Cisco
Caesarea, Israel
4d
Design complex PCB layouts for high-speed AI hardware platforms, solving placement and routing challenges for signals and power networks.
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Staff Digital Design Engineer
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Analog Devices
Valencia, Valencian Community, Spain
$135k
4d
Lead complex digital design projects and provide technical leadership for system-level architecture.
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STA Engineer
Apple
Beaverton, United States of America
4d
Lead timing closure and verification for Apple SoC chips in deep sub-micron technologies for high-end mobile applications.
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Hardware Design Engineer – High-Speed PCB / Signal Integrity
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Oxigent Technologies
Barcelona, Catalonia, Spain
€48k
4d
Designing high-complexity embedded PCBs for next-gen vehicle infotainment and connectivity systems, integrating microprocessors, FPGAs, and high-speed interfaces.
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Prácticas en Ingeniería FPGA
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Exceltic
Valencian Community, Spain
4d
Design and verification of digital systems based on FPGA for industrial, automotive, aerospace, and critical systems applications.
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FY27 Intern - Digital Design Engineering Intern - Canada (16 months)
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Qualcomm
Toronto, ON, CA
$55k
4d
Intern role focused on end-to-end exposure across IC design and DFT processes, including RTL coding, validation, and silicon bring-up for custom SoCs and IPs.
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Staff Implementation Engineer
Arm
Multiple locations
4d
Develop physical implementations of Arm solutions for AI compute, secure compute, large-screen devices, infrastructure, and automotive markets, optimizing power and performance from RTL to GDSII.
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Camera Subsystem Integration Lead
Qualcomm
San Diego, California, United States of America
4d
Lead the integration of Camera and Image Processing subsystems into next-generation SoCs, defining architecture, interfaces, and driving RTL integration across multiple IPs.
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Senior/Lead VLS Engineer - Global Circuits
Sambanovasystems
San Jose, CA
$210k–$280k
4d
Architect and design custom ultra-low-jitter, low-skew clock distribution networks and power integrity solutions for advanced AI accelerator chips.
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マイコン/SoC向けシステム制御サブシステム開発エンジニア
Renesas-Electronics
Kodaira, jp
5d
Develop system control subsystems (SYSSS) for microcontrollers and SoCs, including reset, clock, and low-power mode functions to support chip-wide operations.
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MCU/SoC System Control Subsystem Development Engineer
Renesas-Electronics
Kodaira, jp
5d
Develop System Control Subsystems (SYSSS) for microcontrollers (MCUs) and SoCs, governing overall chip operation including reset, clock management, and low-power modes.
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Sr Principal Engineer of SoC/MCU Architecture
Renesas-Electronics
Kodaira, jp
5d
Define SoC/MCU architectures and detailed technical specifications for high-performance chips used in autonomous driving systems, ensuring compliance across verification, validation, and testing.
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Senior RTL Design Engineer – FPGA/ASIC Design
Advanced Micro Devices, Inc
Hyderabad, India
5d
Design, develop, integrate, and validate complex digital hardware solutions targeting FPGA and Adaptive SoC platforms, including RTL design, DSP algorithms, and system-level emulation.
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Staff Digital Design Engineer (资深/高级数字前端工程师)
Renesas-Electronics
Shanghai, cn
5d
Design and verify digital logic within mixed-signal ICs, handling backend tasks like synthesis, timing closure, and DFT for new product development.
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Backend Physical Design Engineer
Broadcom
IND-Bangalore Electronic City - S1, IN
5d
Lead Broadcom's backend physical design methodology to achieve right-first-time silicon for SoCs in 5nm and lower technologies.
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System Application Engineer - Hardware
NVIDIA
Taiwan, Taipei
5d
System-level hardware project development and debugging for ARM- and X86-based platforms integrating NVIDIA solutions.
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RTL Engineer – Physical AI Solutions
Altera
San Jose, California, United States
$149k–$238k
5d
Designing, implementing, and verifying high-performance digital logic (RTL) for FPGA and programmable hardware solutions that accelerate Physical AI workloads.
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Physical Design Engineer
Apple
Cupertino, United States of America
$216k–$325k
5d
Drive physical aspects of complex digital logic blocks early in the design cycle, from floor planning to GDS2 implementation and sign-off.
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Senior FPGA Engineer
Cisco
San Jose, California, US
$155k
5d
Design and develop FPGA-based hardware platforms for Cisco's core Switching, Routing, and Wireless products to power AI-era data centers.
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SSD Systems Architect - Principal/MTS/SMTS/DMTS
Micron
Boise, Idaho, United States of America
$153k–$351k
5d
Define innovative SSD architectures, develop product specifications, and model performance/power for next-gen memory solutions.
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Senior SoC Architect, RAS
NVIDIA
US, CA, Santa Clara
$184k–$288k
5d
Define and drive SoC-level Reliability, Availability, and Serviceability (RAS) hardware architecture for advanced CPUs and SoCs, ensuring system resiliency, observability, and debuggability for datacenters, autonomous vehicles, and edge systems.
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Physical Design Engineer
Apple
Cupertino, United States of America
$150k–$225k
5d
Contribute to all phases of physical design for high-performance PHYs from RTL to GDSII delivery, focusing on timing, power, and area optimization.
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Physical Design Engineer
Apple
Austin, United States of America
5d
ASIC Block level physical design for GPU chips, covering floor planning, placement, clock tree synthesis, routing, timing closure, and physical verification.
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Front End Design Engineer
Apple
Austin, United States of America
5d
Convert RTL designs into netlists, optimize power/performance/area, and ensure design robustness and correctness for chip development.
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Physical Design Engineer
Apple
Cupertino, United States of America
$150k–$225k
5d
Drive physical aspects of chip partitions early in the design cycle, completing netlist to GDS2 implementation and ensuring signoff closure.
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Silicon Prototype Engineer
Apple
Cupertino, United States of America
$221k–$278k
5d
Responsible for the complete lifecycle of FPGA platforms, from architecture and hardware selection to implementation, bring-up, and pre-silicon validation.
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FE Engineer
Apple
San Diego, United States of America
$157k–$214k
5d
Define microarchitecture, design RTL in SystemVerilog/Verilog, and integrate/verify IP for high-speed communication systems.
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Physical Design Engineer
Apple
Beaverton, United States of America
5d
Physical design implementation of partitions and top-level chips, including place and route flows, floor planning, and timing closure.
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Physical Design Engineer
Apple
Cupertino, United States of America
$174k–$225k
5d
Drive physical design and timing closure for large complex SoC designs and core platforms, from RTL to GDS2 implementation.
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