Product Engineer - STA
Core
Develop and optimize placement, CTS, and routing flows for 7nm and 5nm semiconductor designs using Aprisa tools while providing expert technical support and training to customers.
Role type
Senior IC physical design engineer (place and route)
Builds
Aprisa place and route tool flows and methodologies for chip design
Domain
Semiconductor design automation (EDA)
Required skills
Physical design (floorplan, placement, CTS, routing), Static Timing Analysis (STA), timing/power/area optimization, commercial place and route tools (Synopsys-ICC2, Cadence-Innovus, Aprisa), tapeout experience, AI-assisted scripting
Preferred skills
Static Timing Analysis (STA) tools (PrimeTime, Tempus), multiple voltage islands, top-level floor-planning, chip-assembly
Technologies
Aprisa, Synopsys-ICC2, Cadence-Innovus, PrimeTime, Tempus, Copilot
Responsibilities
Develop and optimize placement, CTS, and routing flows for complex block and full-chip designs; Provide expert technical support and training to customers deploying Aprisa tools; Solve critical design problems to achieve performance, area, and power targets; Identify and resolve timing, power, and area trade-offs; Collaborate with R&D teams to develop signoff-ready ECO flows; Triage and resolve customer issues and JIRAs; Leverage AI tools to optimize workflows and automate tasks
Seniority
Mid-level, hands-on IC
