Senior Engineer, SoC PnP Architect
Core
Senior SoC PnP Architect responsible for system-level performance, power, and efficiency investigations across complex silicon platforms, bridging pre-silicon modeling, emulation, and post-silicon characterization.
Role type
Senior IC SoC Performance and Power (PnP) Architect
Builds
SoC architecture decisions, IP configuration, memory/interconnect sizing, QoS strategy, and platform-level optimization
Domain
Semiconductor industry, System-on-Chip (SoC) architecture, Performance and Power
Required skills
SoC performance architecture, pre-silicon performance analysis, simulation and hardware emulation (Palladium, Veloce, ZeBu), cycle-accurate/transaction-level modeling, waveform-based debug, latency/bandwidth/throughput characterization, CHI/AXI/PCIe/CXL protocol debug, SystemC/TLM modeling, model-to-silicon correlation, post-silicon characterization, root-cause analysis, Linux/bare-metal profiling, computer architecture (CPU/GPU/NPU), C/C++/Python
Technologies
Palladium, Veloce, ZeBu, SystemC, TLM, Linux, perf, ftrace, C++, Python
Responsibilities
Drive system-level performance, power, and efficiency investigations; Develop and calibrate performance/power models; Support silicon bring-up and post-silicon characterization; Identify system-level bottlenecks; Translate modeling insights into architectural recommendations; Lead cross-functional investigations.
Seniority
Senior, hands-on IC