Senior PD Engineer - STA & Timing Closure
Core
Plan and execute full chip timing activities and signoff for advanced chiplets in latest technologies.
Role type
Senior IC physical design engineer (STA & Timing Closure)
Builds
Advanced chiplets in latest technologies
Domain
Semiconductor / Digital IC Design
Required skills
Fullchip timing analysis, Floor-planning, Place & route, Power and clock distribution, Pin placement, Timing debugging, TCL/Perl scripting, Primetime, ICC2
Preferred skills
Synthesis, DFT, Constraints analysis (GCA), 3nm or finer geometries experience
Technologies
Primetime, ICC2, GCA, TCL, Perl
Responsibilities
Perform fullchip timing analysis for multiple modes including Functional, DFT, and interface special timing checks; Debug timing issues at fullchip and block levels; Execute floor-planning, place & route, power, and clock distribution; Interact with design teams, CAD teams, and tool vendors
Seniority
Senior, hands-on IC
