ASIC Physical Design Engineer - New College Graduate
Core
Responsible for the stage from RTL frozen to tape out, including synthesis, formal verification, constraints definition, and timing closure/sign-off for digital chips.
Role type
ASIC Physical Design Engineer (New College Graduate)
Builds
High-performance, low-power digital chips for AI, GPUs, and accelerated computing.
Domain
Semiconductor / VLSI Design
Deliverable
production ML models
Required skills
RTL design, Synthesis, Formal verification, Timing closure, Constraints creation, Floorplanning, Netlist generation, EDA tool usage (Synopsys/Cadence), Python/TCL scripting
Preferred skills
Advanced process technology knowledge, Flow automation development, Methodology development
Technologies
Synopsys DC/PT/Formality, Cadence RC compiler/LEC, Python, TCL
