ASIC Physical Design Engineer
Core
Design and implementation of 100 ~ 400 million gate integrated circuits in 7nm/5nm/3nm/2nm process technologies using commercial and in-house EDA tools.
Role type
Senior ASIC Physical Design Engineer
Builds
Integrated circuits (GPU/CPU/DSP architectures)
Domain
Semiconductor / VLSI Design
Required skills
RTL to GDS flow, placement, clock tree synthesis, detailed routing, physical verification, formal verification, timing analysis, EDA tools (Synopsys, Cadence, Siemens), GPU/CPU/DSP architecture knowledge
Preferred skills
UNIX/Linux proficiency, scripting languages
Technologies
Synopsys, Cadence, Siemens, 7nm, 5nm, 3nm, 2nm
Responsibilities
Perform RTL synthesis, placement, clock tree synthesis, detailed routing, physical verification, formal verification, and timing analysis for large-scale ICs.
Seniority
Senior, hands-on IC
