ASIC Engineer || Physical Design, CAD Methodology || STA Setup, Convergence Methodology || Exp 4+ years
Core
Physical Design Engineer responsible for backend implementation of complex networking chips from RTL to GDS, focusing on timing closure, power integrity, and performance optimization.
Role type
Senior IC ASIC Physical Design Engineer
Builds
Next-generation networking chips for Enterprise and Service Provider solutions
Domain
Semiconductor / ASIC Design / Networking Hardware
Required skills
Hierarchical floor planning, Place & route, Static timing analysis (STA) setup and convergence, Power integrity analysis, Clock and power distribution, I/O planning, Hard IP integration, Timing ECO implementation, Automation script development, Large-scale design implementation (>100M gates)
Preferred skills
CTS strategy development, Physical design flow and tool methodology optimization, Multi-mode and multi-corner design sign-off, Timing ECO flow enablement (Tweaker/Primetime)
Technologies
STA tools, Primetime, Tweaker, GDS, RTL, 16/14/7/5/3/2nm process nodes
Responsibilities
Drive backend process through RTL to GDS implementation flow, Perform timing closure and physical verification, Optimize performance and die size, Develop automation scripts for STA methodology, Conduct power integrity analysis, Execute timing ECO implementation strategies
Seniority
Senior, hands-on IC
