Senior ASIC Timing Engineer, DFT
Core
Drive timing analysis and closure for DFT logic on all Nvidia chips (GPUs/CPUs/DPUs/LPUs/SoCs) at all hierarchical levels.
Role type
Senior ASIC Timing Engineer (DFT)
Builds
GPUs, CPUs, DPUs, LPUs, SoCs
Domain
Semiconductor / ASIC Design
Deliverable
production ML models
Required skills
Static Timing Analysis (STA), timing constraints development, ECO implementation, DFT logic analysis, timing convergence tools, automation workflow development
Preferred skills
Serdes domain STA, Processor/IO/SMVA domain STA, methodology development
Technologies
Industry standard timing convergence tools
Responsibilities
Drive timing analysis and closure for DFT logic; Work with PD, DFX, Clocks teams to develop timing closure strategy and constraints; Implement ECOs for timing and power convergence; Improve workflows by introducing automation and standardization
