Master Thesis: Early Prediction and Optimization of power, Perfomance and Area
Core
Investigate how RTL characteristics and simulation data can improve early prediction of Power, Performance, and Area (PPA) for digital designs.
Role type
Master's thesis researcher (digital design optimization)
Builds
A reusable methodology or prototype flow for early PPA feedback
Domain
Semiconductor design, digital logic, computer architecture
Deliverable
production ML models
Required skills
RTL design (Verilog/SystemVerilog/VHDL), digital design and computer architecture, experimental data analysis, synthesis configuration evaluation
Preferred skills
Logic synthesis/ASIC flows, digital simulation (VCD/FSDB), Python/Tcl scripting, data analysis, machine learning/AI methods
Technologies
Verilog, SystemVerilog, VHDL, Python, Tcl, VCD, FSDB
