PCIe Design Engineer
Core
Designing PCIe subsystems and SoCs for Broadcom ASIC products, focusing on high-speed interface protocols and silicon bring-up.
Role type
Senior IC digital ASIC design engineer (PCIe)
Builds
PCIe Gen6/7 subsystems and System-on-Chip (SoC) designs
Domain
Semiconductor / VLSI / High-speed serial interfaces
Required skills
PCIe Gen6/7 protocol design, VLSI architecture, RTL coding, Serdes/PLL design, Silicon debug, Synthesis, timing closure, Equivalence checks (Formality/Conformal), Lint/CDC/RDC tools
Preferred skills
AMBA protocols, DMA, memory organization, processor architecture
Technologies
PCIe, Serdes, PLLs, AMBA, Formality, Conformal, Lint, CDC, RDC
Responsibilities
Develop PCIe subsystems and SoC architectures, perform timing closure and equivalence checks, debug silicon bring-up sequences, provide solutions to design problems
Seniority
Senior, hands-on IC
