RTL Engineer
Core
Designing digital blocks and subsystems for AI accelerators from microarchitecture definition through silicon implementation.
Role type
Senior IC RTL Engineer (AI Accelerators)
Builds
AI accelerator digital blocks and subsystems
Domain
Semiconductor / AI Hardware
Deliverable
production ML models
Required skills
Verilog, SystemVerilog, Microarchitecture, Python, Tcl, Synthesis, Static Timing Analysis (STA), Clock and Power Gating, CDC, Lint
Preferred skills
AI/ML accelerators, Low-power techniques (UPF), High-speed interfaces (HBM, PCIe, SerDes), Advanced nodes (7nm+), RISC-V, CPU design, FPGA prototyping
Technologies
SystemVerilog, Verilog, Python, Tcl, PCIe, AI FPGA Flow
Responsibilities
Own RTL design of accelerator digital blocks and subsystems from microarchitecture definition through implementation; Translate architectural specifications into efficient, synthesizable RTL meeting PPA targets; Make microarchitecture trade-offs for performance and power; Collaborate with DV, PD, and DFT teams; Ensure block-level quality including synthesis, timing, and CDC signoff; Contribute to architecture definition and design reviews; Debug across simulation, emulation, and post-silicon bring-up; Use and develop AI-assisted workflows.
Seniority
Senior, hands-on IC
