IC Design Engineer
Core
Leading team in physical design implementation of large System-On-Chip ASICs (500-800M gates) for computing and networking products.
Role type
Senior IC Design Engineer (Physical Design)
Builds
High-performance System-On-Chip ASICs in 5nm/3nm/2nm process technologies
Domain
Semiconductor / VLSI / ASIC Design
Required skills
Physical design implementation, EDA tools (Cadence, Synopsys, Mentor, Ansys), CPU/DSP architecture knowledge, Timing closure, Perl/Tcl/Python scripting
Preferred skills
Algorithm knowledge, Innovation in design flow/methodology
Technologies
Cadence, Synopsys, Mentor, Ansys, 5nm, 3nm, 2nm
Responsibilities
Lead team in physical design implementation of large ASICs, Provide technical support to customers, Collaborate with RTL and Physical Design teams to resolve timing violations, Utilize EDA tools for design and implementation, Participate in design flow and methodology development
Seniority
Senior, hands-on IC
