Sr. EMIR Analysis Engineer
Core
Full chip SoC electrical signoff convergence with physical design engineers to achieve first pass silicon success.
Role type
Senior IC power integrity engineer (ASIC)
Builds
Robust power delivery design and low power/UPF specifications for SoCs
Domain
Semiconductor / ASIC design
Required skills
Power integrity analysis, Power delivery flows, Redhawk tooling, Tcl scripting, Perl scripting, Electrical signoff convergence
Preferred skills
4+ years in power integrity domains, Low power design, UPF specification, CAD flow development
Technologies
Redhawk, Tcl, Perl, UPF, RTL, CAD tools
Responsibilities
Work on full chip IR/EM convergence on multiple ASICs across different technology nodes, Collaborate with architecture, power management, package and floorplan teams to develop robust power delivery design, Partner with RTL and PD teams to define low power and UPF specifications for the SoC, Work with CAD teams to develop new flows and methodologies in the power integrity domain
