ASIC Design Engineer, High Speed IO
Core
Design and implement High Speed IO IP (USB, UFS, Ethernet, PCIe) for next-generation automotive chips.
Role type
Senior RTL Design Engineer (High Speed IO)
Builds
High Speed IO IP blocks for automotive SoCs
Domain
Semiconductor / Automotive Electronics
Required skills
RTL design, digital design fundamentals, micro-architecture, timing closure, silicon validation support, system security architecture knowledge
Preferred skills
Security standards and protocols, cross-cultural collaboration, debugging, analytical problem solving
Technologies
USB, UFS, Ethernet, PCIe, RTL, SoC
Responsibilities
Own micro-architecture and RTL development of design modules, Micro-architect features to meet performance, power and area requirements, Work with HW architects to define critical features, Work with verification teams to verify the correctness of implemented features, Partner with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable
Seniority
Mid-level, hands-on IC
