ASIC Power Design Engineer II (Full Time) - United States
Core
Implement and optimize low-power design methodologies and perform power analysis/estimation for ASICs powering Cisco's core Switching, Routing, and Wireless products.
Role type
Senior IC ASIC Power Design Engineer
Builds
Low-power hardware platforms for AI-era networking switches, routers, and wireless access points
Domain
Semiconductor / ASIC Design / Low-Power Design
Required skills
Low-power design methodologies (UPF/CPF, clock gating, power gating, multi-Vt, DVFS), Power analysis tools (Synopsys PrimePower), Hardware description languages (SystemVerilog/Verilog), Scripting (Python/TCL/Perl), Advanced process nodes (FinFET/GAA)
Preferred skills
Activity-driven power analysis (FSDB/VCD/SAIF), EDA tools (Design Compiler, Fusion Compiler, Prime Time, StarRC, Calibre), Power integrity/IR-drop/EM analysis (Ansys RedHawk/Voltus), FinFET/GAA library architectures
Technologies
Synopsys PrimePower, Synopsys Design Compiler, Synopsys Fusion Compiler, Synopsys Prime Time, Synopsys StarRC, Siemens Calibre, Ansys RedHawk, Ansys Voltus, SystemVerilog, Verilog, Python, TCL, Perl, Linux/Unix
Responsibilities
Implement low-power design methodologies (clock gating, power gating, multi-Vt, DVFS), Perform block- and full-chip-level power analysis and estimation, Collaborate with RTL design and architecture teams to identify power bottlenecks, Achieve timing closure, signal integrity, and power targets, Develop automated design and analysis workflows, Participate in post-silicon power and performance validation
Seniority
Mid-Senior, hands-on IC
