Technical Lead Digital Design Engineer
Core
Design and implement next-generation digital designs for high-performance connectivity solutions, covering micro-architecture through silicon bring-up.
Role type
Senior IC digital design engineer (high-speed protocols)
Builds
High-performance connectivity chips (CXL, Ethernet, NVLink, PCIe, UALink) for hyperscalers and ecosystem partners
Domain
Semiconductor / High-speed digital design
Required skills
SystemVerilog, Synopsys/Cadence synthesis, high-speed protocol design (PCIe, Ethernet, DDR), static-timing analysis, clocking/CDC/RDC, Python scripting, UVM verification basics, IP integration
Preferred skills
Embedded firmware development, RISC-V/Arm subsystems, production DFT experience
Technologies
SystemVerilog, Python, Synopsys, Cadence, UVM, PCIe, Ethernet, DDR, CXL, NVLink, UALink
Responsibilities
Own RTL implementation from micro-architecture to sign-off; Collaborate with verification teams on test plans and debugging; Support timing closure and DFT implementation; Develop automation scripts for ASIC methodology improvement
Seniority
Senior, hands-on IC
