Senior Product Engineer - STA
Core
Senior Product Engineer specializing in Static Timing Analysis (STA) and physical design flows for 7nm and 5nm semiconductor chip designs.
Role type
Senior IC Product Engineer (Physical Design & STA)
Builds
Aprisa place and route tool flows and methodologies for complex block and full-chip designs
Domain
Semiconductor / Electronic Design Automation (EDA)
Deliverable
production ML models | product features
Required skills
Physical Design (floorplan, placement, CTS, routing), Static Timing Analysis (STA), timing/power/area optimization, commercial EDA tools (Synopsys-ICC2, Cadence-Innovus, Aprisa), tapeout experience, AI-assisted scripting
Preferred skills
PrimeTime, Tempus, multiple voltage islands, top-level floor-planning, chip-assembly
Technologies
Aprisa, Synopsys-ICC2, Cadence-Innovus, PrimeTime, Tempus, Copilot
Responsibilities
Develop and optimize placement, CTS, and routing flows; Provide expert technical support and training to customers; Solve critical design problems to meet performance, area, and power targets; Collaborate with R&D to develop signoff-ready ECO flows; Triage and resolve customer issues and JIRAs; Leverage AI tools to optimize workflows and automate tasks
Seniority
Senior, hands-on IC
