ASIC Design Engineer, High Speed IO
Core
Design and verify High Speed IO IP blocks (UFS, Ethernet, PCIe, USB) for next-generation automotive chips.
Role type
Senior RTL Design Engineer (High Speed IO)
Builds
High Speed IO IP units for automotive SoCs
Domain
Semiconductor / Automotive / High Speed Interfaces
Required skills
RTL design, digital design fundamentals, micro-architecture, timing closure, silicon validation support, protocol implementation
Preferred skills
HSIO standards knowledge, AI tools exposure (Claude, Cursor)
Technologies
UFS, Ethernet, PCIe, USB, RTL, VLSI
Responsibilities
Own micro-architecture and RTL development of design modules, Micro-architect features to meet performance, power and area requirements, Work with HW architects to define critical features, Partner with verification teams to verify the correctness of implemented features, Collaborate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable
Seniority
Mid-level, hands-on IC
