Sr. Principal VLSI/ ASIC Design Engineer
Core
Lead early-stage ASIC architecture, RTL design, and implementation for complex networking, compute, and SoC applications.
Role type
Sr. Principal VLSI/ASIC Design Engineer (Hands-on IC with technical leadership)
Builds
Networking, compute, and System-on-Chip (SoC) solutions
Domain
Semiconductor / Hardware Design
Required skills
ASIC/VLSI design principles, RTL design (Verilog/System Verilog), SoC development, architecture definition, synthesis, timing analysis, physical design interaction, design signoff, performance/power/area tradeoff analysis, design methodology definition, cross-functional collaboration, technical mentorship
Preferred skills
Networking ASICs, high-speed interfaces, packet-processing pipelines, formal verification, low-power design, DFT, IP vendor/foundry experience
Technologies
Verilog, System Verilog, Synthesis tools, Simulation tools, Physical design tools
Responsibilities
Define architectural approaches and microarchitectures aligned with product roadmaps; Design and modify complex RTL blocks; Drive RTL implementation through synthesis to production readiness; Analyze design tradeoffs for performance, power, area, and scalability; Conduct design reviews for compliance and quality; Mentor less-experienced engineers; Collaborate with architecture, verification, physical design, and manufacturing teams; Identify emerging technologies and innovations.
Seniority
Principal, technical authority & mentorship
