IC Design Engineer (DFT)
Core
Define chip-level DFT architecture and implement test schemes (scan, BIST, MBIST) for 5nm/3nm ASIC designs.
Role type
IC Design Engineer (DFT)
Builds
ASIC designs with embedded test infrastructure
Domain
Semiconductor / Digital IC Design
Required skills
DFT methodology (BIST, SCAN, JTAG, ATPG), RTL analysis, synthesis constraints, static timing analysis (STA), ATE bring-up, simulation, physical design
Preferred skills
Multi-mode/multi-corner STA, Sign-Off Checks, Mentor/Synopsys DFT flow expertise
Technologies
Mentor, Synopsys
Responsibilities
Participate in chip level DFT architecture definition; Implement basic DFT schemes including scan, boundary scan, MBIST, Logic BIST and SSN; Verify all DFT logics and test patterns with simulation; Perform test modes static timing analysis; Participate in ATE bring-up and debug the DFT patterns on ATE.
Seniority
Mid-Senior, hands-on IC
