Senior Lead Design Engineer - RTL Design
Core
Lead RTL architecture, microarchitecture, and implementation for complex FPGA, programmable SoC, and infrastructure-class subsystems, translating system requirements into robust microarchitectures and guiding execution from concept through product readiness.
Role type
Senior Lead Design Engineer - RTL Design (Hands-on IC with technical leadership)
Builds
High-performance, reusable RTL for programmable devices and platform solutions
Domain
Semiconductor / FPGA / ASIC / SoC
Required skills
Verilog, SystemVerilog, RTL design, synthesis, CDC/RDC, formal checking, timing constraints, high-performance digital subsystem design, architectural tradeoffs, technical planning, risk management
Preferred skills
FPGA architecture design, reusable RTL IP, high-bandwidth memory architectures, FPGA prototyping/emulation, Python/Tcl/Perl scripting, technical leadership via patents/publications
Technologies
Verilog, SystemVerilog, Python, Tcl, Perl, shell
Responsibilities
Lead RTL architecture and implementation for complex subsystems; Own RTL design for critical blocks ensuring reusability and timing closure; Define design specifications and implementation plans; Drive technical tradeoffs across performance, power, and area; Establish RTL design methodologies and coding standards; Partner with verification to shape strategy and drive closure; Collaborate with physical design, CAD, and post-silicon teams; Lead root-cause analysis of complex design issues; Provide technical mentorship and conduct architecture reviews.
Seniority
Senior, hands-on IC with technical leadership
