Principal PCS/PMA RTL Design Engineer
Core
Design and implement synthesizable RTL for Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) logic in high-speed interconnect standards (Ethernet, PCIe, UCIe, UALink) for AI and cloud infrastructure ASICs.
Role type
Principal RTL Design Engineer (High-Speed Interconnect/PHY)
Builds
High-performance connectivity and networking ASICs
Domain
Semiconductor, High-Speed Interconnect, Networking
Required skills
Verilog/SystemVerilog RTL development, high-speed serial protocol knowledge (Ethernet/PCIe/UCIe/UALink), digital design fundamentals (state machines/datapaths/FIFOs), RTL simulation and debugging, synthesis and timing analysis, ASIC design flow collaboration
Preferred skills
PCS/PMA/PHY digital logic design experience, PAM4 signaling and FEC implementation, link training and equalization control, multi-lane SerDes datapaths, synthesis/implementation tools (Cadence/Synopsys), STA tools, UVM verification, scripting for automation, advanced-node CMOS tapeout experience
Technologies
Verilog, SystemVerilog, UVM, Cadence Genus/Innovus, Synopsys Design Compiler/ICC2, PrimeTime/Tempus, Python, Tcl, Perl, Shell
Responsibilities
Develop synthesizable RTL for PCS/PMA blocks including line encoding, scrambling, alignment, and FEC; Implement PMA digital interface logic including CDR control, equalization, and link training; Design lane-level logic including bonding, deskew, and BIST; Collaborate with verification teams on test plans, coverage goals, and debug simulation failures; Support logic synthesis, constraints, and timing closure; Participate in silicon bring-up, interoperability testing, and post-silicon debug
Seniority
Principal, hands-on IC
