Design Implementation Synthesis Engineer, Sr Lead
Core
Senior lead responsible for RTL-to-gate synthesis, low-power design flows, and formal verification for hardware chips.
Role type
Senior IC Design Implementation Synthesis Engineer
Builds
Integrated silicon chips with optimized power and timing
Domain
Semiconductor hardware design
Required skills
Synthesis (Synopsys Design Compiler, DCG, Fusion Compiler, Cadence RC, Genus), Multi-voltage design, Power-aware synthesis, UPF flows, Formal verification (Cadence LEC, Synopsys Formality), Timing constraint writing, Perl/TCL scripting, Makefile flows
Preferred skills
RTL design integration, Masters in Electronics/Electrical Engineering
Technologies
Synopsys Design Compiler, DCG, DC_NXT, Fusion Compiler, Cadence RC, Genus, Cadence LEC, Synopsys Formality, Perl, TCL
Responsibilities
Develop and debug synthesis flows for low-power designs, Write and debug timing constraints, Perform formal verification, Script flows using Perl/TCL, Drive designs from RTL through commercialization
Seniority
Senior, hands-on IC
