CareerPlan

Physical Design Engineer

Cupertino, United States of AmericaFull-time$150k–$225k2026-11-05 → 2026-11-10

Core

Drive physical aspects of chip partitions from netlist to GDS2, ensuring timing, physical, and electrical closure while optimizing for power density and area.

Role type

Senior IC physical design engineer (VLSI)

Builds

Large-scale integrated circuits (chips)

Domain

Semiconductor / VLSI

Required skills

VLSI design, CMOS fundamentals, Place and Route (PnR), Static Timing Analysis (STA), Physical Design Verification (DRC, LVS, Antenna), Verilog coding, standard cells, compiled memories

Preferred skills

N/A

Technologies

Verilog, GDS2

Responsibilities

Collaborate with logic design teams to understand partition architecture; Complete netlist to GDS2 implementation; Perform timing, physical, and electrical verification; Resolve and improve design and flow issues; Explore and implement low power techniques; Optimize designs for area to achieve a low area footprint.

Seniority

Mid-level, hands-on IC