Senior/Staff Physical Design Engineer
Core
Senior Block Coordinator responsible for planning, execution, and closure of 15+ ASIC/SoC blocks using Cadence Innovus.
Role type
Senior IC physical design engineer (block level)
Builds
ASIC/SoC blocks for product companies
Domain
Semiconductor, ASIC Physical Design
Required skills
Cadence Innovus, Tcl scripting, timing closure, congestion debugging, DRC/LVS signoff, cross-team coordination
Preferred skills
Python, Perl, Shell, advanced node experience (2/3/4/6nm), STA/DFT/Synthesis knowledge
Technologies
Cadence Innovus, Tcl, Python, Perl, Shell
Responsibilities
Plan and execute closure of 15+ blocks, drive timing closure (setup/hold), debug congestion and routability, coordinate with signoff teams for DRC/LVS/SI/IR/EM closure, automate flows with Tcl
Seniority
Senior, hands-on IC
