Staff Digital Design Engineer
Core
Design and develop digital components of high-performance DDR PHY for LPDDR/DDR memory interfaces used in leading-edge SoC products.
Role type
Staff IC digital design engineer (memory interface)
Builds
High-performance DDR PHY IPs for next-generation SoC products
Domain
Semiconductor / Hardware Design
Required skills
RTL development (Verilog/SystemVerilog), micro-architecture definition, linting, clock-domain crossing (CDC), reset-domain crossing (RDC), low-power design, synthesis, static timing analysis (STA), Design-for-Test (DFT), silicon bring-up, debugging complex digital IPs
Preferred skills
DDR/LPDDR PHY experience, high-speed interface development, UPF and power-aware design methodologies, scan insertion, ATPG, post-silicon validation
Technologies
Verilog, SystemVerilog, UPF, EDA tools for RTL design and verification
Responsibilities
Design and develop digital components of high-performance DDR PHY for LPDDR/DDR memory interfaces; Participate in micro-architecture definition, RTL coding, integration, and debug of complex digital IPs; Drive RTL quality and signoff through lint, clock-domain crossing (CDC), reset-domain crossing (RDC), low-power, and design rule checks; Collaborate with the functional verification team to develop verification plans, review coverage closure, and debug design issues; Develop synthesis and timing constraints, analyze timing reports, and deliver high-quality netlists for physical design implementation; Create and maintain UPF-based low-power intent and perform equivalence checking, and low-power signoff; Implement and validate Design-for-Test (DFT) features, support scan insertion, ATPG generation, and optimize stuck-at and transition fault coverage; Support pre-silicon and post-silicon bring-up, characterization, debug, and issue resolution across multiple product programs; Contribute to methodology improvements, automation, and design flow enhancements to improve engineering productivity and quality
