Physical Design Engineer
Core
Build full chip clock trees, perform specification generation, and clock planning involving design and construction of recombinant networks for high-performance CPU cores.
Role type
Physical Design Engineer (Chip Design)
Builds
Full chip clock trees and clock distribution networks for high-performance CPU cores
Domain
Semiconductor / Chip Design / Physical Design
Required skills
clock tree synthesis, specification generation, clock planning, recombinant network design, static timing analysis, physical design verification, place and route methodology, interconnect delay analysis, parasitics analysis, coupling analysis, FinFET technology, GAA technology, EDA tool usage (Synopsys, Cadence), PPA optimization
Technologies
Synopsys, Cadence, FinFET, GAA
Responsibilities
Build full chip clock trees, perform specification generation, clock planning involving design and construction of recombinant networks, automate clock tree specification generation, work with logic design team to understand partition architecture, complete netlist to GDS2 implementation, conduct timing, physical and electrical verification, resolve design and flow issues related to physical design
Seniority
Mid-level, hands-on IC
