Senior Design Engineer
Core
Develop and optimize mixed-signal and high-speed IPs for integration into full-chip designs.
Role type
Senior IC logic design engineer (FPGA/RTL)
Builds
IP blocks, functional units, and subsystems for full-chip integration
Domain
Semiconductor / FPGA / Digital Logic
Required skills
RTL coding, System Verilog, simulation (VCS/Synopsys), linting, synthesis, C/C++/Perl/Python/TCL/Unix scripting
Preferred skills
FPGA design and programming, RTL validation
Technologies
VCS, Synopsys, Lint, System Verilog, C, C++, Perl, Python, TCL, Unix Shell
Responsibilities
Develop logic design and RTL coding for IP blocks, create design and simulation examples, integrate IP into full-chip designs, perform hardware bring-up and debugging
Seniority
Senior, hands-on IC
