Physical Design Engineer
Core
Managing the complete netlist-to-GDSII implementation process for design partitions, ensuring timing analysis, physical and electrical verification, and signoff closure.
Role type
Senior IC physical design engineer (SoC ASIC)
Builds
SOC ASICs
Domain
Semiconductor / Hardware Design
Required skills
Physical design concepts and flows, Automatic Place and Route (PnR), Logic placement and routing optimization, Floorplanning, IO and Macro placement, Clocking strategies, Static Timing Analysis (STA), Design Rule Check (DRC) and Layout Versus Schematic (LVS) verification
Preferred skills
N/A
Technologies
Cadence, Synopsys EDA tools, Synopsys PrimeTime, Cadence Innovus/Tempus, Calibre
Responsibilities
Collaborate with logic design teams to understand partition architecture; Manage netlist-to-GDSII implementation; Perform timing analysis and physical/electrical verification; Drive signoff closure; Analyze micro-architecture specifications; Conduct feasibility analyses on performance, area, timing, and power; Optimize PnR partitions for Power/Performance/Area (PPA)
Seniority
Senior, hands-on IC
