Senior Lead Design Engineer
Core
Lead architecture, microarchitecture, and RTL development for complex FPGA, programmable SoC, and infrastructure-class subsystems, focusing on high-throughput datapaths, connectivity, interconnect, and memory access.
Role type
Senior Lead Design Engineer (FPGA/SoC Architecture)
Builds
Next-generation FPGA and programmable SoC solutions for data center, networking, AI, and edge applications
Domain
Semiconductor / FPGA / SoC / Digital Logic
Required skills
Verilog, SystemVerilog, RTL design, synthesis, timing closure, high-performance digital architectures, PPA tradeoffs, cross-functional leadership
Preferred skills
FPGA prototyping, emulation, silicon bring-up, Python/Tcl/Perl scripting, reusable IP development, technical mentorship
Technologies
Verilog, SystemVerilog, Python, Tcl, Perl, FPGA, SoC, ASIC
Responsibilities
Lead architecture and RTL development for complex subsystems; Define technical requirements and implementation plans; Drive technical tradeoffs across performance, power, area, and latency; Own critical blocks through full development lifecycle; Establish reusable design IP and automation; Partner with verification, physical design, and software teams; Provide technical mentorship and guidance
Seniority
Senior, hands-on IC with technical leadership
