Lead Design Engineer
Core
Lead physical design implementation for ASIC chips at advanced technology nodes, ensuring timing, power, and signal integrity closure.
Role type
Senior IC physical design engineer (ASIC)
Builds
ASIC chips (low power, high speed)
Domain
Semiconductor / VLSI Design
Required skills
hierarchical physical design, floor planning, place and route, clock tree synthesis, timing closure, power grid design, DRC/LVS/Antenna verification, EM/IR signoff, DFM closure, low power design, static timing analysis, formal verification
Preferred skills
deep sub-micron technology expertise, RTL design collaboration
Technologies
Cadence tools, ASIC design flow
Responsibilities
Perform physical design implementation including floor planning, place and route, and signoff; Lead next generation physical design methodology and flow development; Collaborate with RTL design teams to ensure successful tapeouts.
Seniority
Senior, hands-on IC
