Senior CAD And Methodology Design Engineer
Core
Design engineer supporting and optimizing the RTL-to-GDS design flow for semiconductor projects in the Adaptive & Embedded Computing Group.
Role type
Senior IC design engineer (CAD & methodology)
Builds
Standardized RTL-to-GDS design flows and tool methodologies for chip development
Domain
Semiconductor / Digital IC Design
Required skills
RTL-to-GDS flow expertise, TCL scripting, Python scripting, synthesis, place-and-route, static timing analysis, PDK enablement, physical signoff (DRC/LVS/DFM/EM/IR), low-power methodology
Preferred skills
Fusion Compiler, IC Compiler, Innovus, PrimeTime, SDC, Calibre, Totem, Redhawk, UPF
Technologies
Fusion Compiler, IC Compiler, Innovus, PrimeTime, Calibre, TCL, Python, PERL
Responsibilities
Support CAD infrastructure team on RTL-to-GDS flow, maintain standardized design flows, implement customized flows for Fabric design groups, work with external tool vendors, develop tool-flow methodologies, debug bugs in implementation flow, build flows in TCL and Python
Seniority
Senior, hands-on IC
