Sr Staff Engineer-DFT
Core
Define DFT architecture and implementation for blocks within complex SoCs, including hierarchical DFT, test modes, and clocking for next-generation optical DSP chips.
Role type
Sr Staff IC DFT Engineer
Builds
Industry-leading ASICs for hyperscale data center, enterprise, and AI infrastructure markets
Domain
Semiconductor / Digital Design for Test (DFT)
Required skills
DFT architecture, hierarchical DFT, ATPG, MBIST/repair, JTAG, at-speed test, DFT timing/STA, IP integration, silicon debugging, mentoring
Preferred skills
High-speed SerDes/DSP products, advanced nodes (7nm and below)
Technologies
TSMC advanced process nodes, SerDes, PLL, memories, third-party IP
Responsibilities
Define DFT architecture and implementation for a block within the chip; Plan, partition and integrate IP-level DFT; Drive ATPG coverage, test-time and pattern-count targets; Lead DFT sign-off; Debug silicon; Mentor junior engineers; Improve methodology and automation
Seniority
Sr Staff, hands-on IC with mentorship
