Senior Digital Design Engineer
Core
Design and implement digital blocks in Verilog/SystemVerilog for next-generation power management solutions targeting AI, Cloud, and Data Center applications.
Role type
Senior IC digital design engineer
Builds
Power management ICs for AI, Cloud, and Data Center applications
Domain
Semiconductor / Power Management
Required skills
Verilog, SystemVerilog, RTL design, synchronous digital design, finite state machines, clocking strategies, timing analysis, synthesis, clock domain crossing
Preferred skills
Mixed-signal ICs, power management applications, digital control algorithms, Python/Tcl scripting, FPGA prototyping
Technologies
Verilog, SystemVerilog, Python, Tcl
Responsibilities
Design and implement digital blocks, contribute to microarchitecture definition, collaborate with verification and analog engineers, perform simulations and debug design issues, run lint and clock domain crossing checks, support synthesis and timing analysis
Seniority
Senior, hands-on IC
