Physical Design Engineer II
Core
Deliver high-quality physical design tasks including design planning, synthesis, placement, clock tree synthesis, static timing analysis, physical verification, IR drop, EM check, and formal equivalence checks at block, sub-chip, and full-chip levels.
Role type
Senior IC physical design engineer
Builds
Integrated circuits (ICs) and semiconductor chips
Domain
Semiconductor / VLSI Physical Design
Required skills
Static Timing Analysis (STA), Place and Route (PNR), Clock Tree Synthesis, IR drop analysis, Electromigration (EM) analysis, Formal Equivalence Checking, Design Planning, Sign-off methodology, Congestion management
Preferred skills
Custom clocking strategies, EMIR convergence strategies, Risk management
Technologies
RHSC, Star-RC, Fusion Compiler, VCLP, Primetime, Formality, Cadence Innovus, Conformal
Responsibilities
Analyze and drive Static Timing Analysis violations and convergence; Deliver best-in-class place and route (PNR) strategies for congestion and timing; Deliver high-quality Electromigration and IR drop sign-off modeling methodology; Provide crisp status of progress, issues, and risks to management.
Seniority
Senior, hands-on IC
