Physical Design Engineer
Core
Drive physical implementation and timing closure for large complex SoC designs and core platforms from RTL to GDS2.
Role type
Senior IC physical design engineer (SoC)
Builds
High-frequency, low-power logic partitions and full chip implementations for Apple products
Domain
Semiconductor / VLSI / SoC design
Required skills
Floor planning, physical synthesis, place and route (P&R), timing closure, power optimization, script development (TCL/Perl/Python), EMIR analysis, physical verification, low power verification
Technologies
ICC, ICC2, Innovus, Synopsys PrimeTime, Voltus, Redhawk, Calibre, Conformal, Formality, VCLP, CLP
Responsibilities
Complete netlist to GDS2 implementation for partitions; Resolve design and flow issues related to physical design; Drive frontend and backend implementation from RTL to gds2; Responsible for hands-on physical implementation and timing closure of core platforms and SoC's; Streamline timing signoff criterions and flows; Drive physical design and timing convergence at block, cluster, and full chip levels
Seniority
Senior, hands-on IC
