Lead engineer Pre-Silicon System Performance
Core
Technical leader owning end-to-end system performance strategy, methodology, and sign-off for complex server-class SoCs, driving architecture-level performance insights and influencing product decisions.
Role type
Senior Staff Engineer (Server SoC Performance)
Builds
Server-class SoCs for data center applications
Domain
Semiconductor / SoC Architecture / Server Systems
Required skills
SoC micro-architecture, memory systems, interconnects, performance methodology, benchmarking, CPU/memory/NoC/IO trade-off analysis, architecture feature translation to performance metrics, system-level debug
Preferred skills
RUMI/emulation-based performance sign-off, cache-coherent interconnects (CHI/ACE), scalable memory hierarchies, high-bandwidth IO subsystems (PCIe/CXL)
Technologies
RUMI, emulation, CHI, ACE, PCIe, CXL
Responsibilities
Own system-level performance sign-off across multiple subsystems and use cases; Define and drive performance methodology and benchmarks for pre-silicon and early silicon platforms; Lead deep-dive investigations involving CPU, memory, NoC, IO, and power-performance trade-offs; Translate architecture features into quantitative performance projections and risks; Influence architecture and design trade-offs; Mentor engineers and act as a technical authority
Seniority
Senior Staff, hands-on IC with significant impact
