Lead STA Engineer
Core
Drive timing closure and synthesis optimization for advanced connectivity SoCs to ensure wireless solutions meet performance, power, and area requirements.
Role type
Senior STA and Synthesis Engineer / STA Lead
Builds
High-performance wireless connectivity SoCs for IoT, automotive, and industrial applications
Domain
Semiconductor / Wireless Connectivity
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Static timing analysis, Synthesis optimization, Multi-Vt optimization, Clock gating, Power optimization, Logic equivalence check, CLP, Setup/hold analysis, Multi-mode multi-corner (MMMC) timing, Clock domain crossing (CDC) analysis, TCL scripting, Perl scripting, Process variations understanding, OCV/SoCV analysis, Low-power design techniques, Digital design fundamentals, CMOS circuit behavior, Clock tree synthesis (CTS), Clock skew optimization, DFT impact analysis
Preferred skills
Experience with Cadence Genus, Experience with Cadence Tempus, Experience with Synopsys PrimeTime, Experience with complex constraints coding, Experience with clocking architecture, Experience with DFT constraint modes, Experience with IO timing constraints coding, Experience with SPI/CAN interfaces, Experience with automated flow development, Experience with regression frameworks, Experience with mixed-signal designs, Experience with multiple process nodes
Technologies
Cadence Genus, Cadence Tempus, Synopsys PrimeTime, TCL, Perl
Responsibilities
Perform static timing analysis and synthesis for connectivity SoCs, Collaborate with design teams to optimize RTL for timing, power, and area, Write SDC constraints across functional and DFT modes, Drive timing closure through physical design flow coordination, Develop and maintain synthesis and STA methodologies and scripts, Mentor junior engineers
Seniority
Senior, hands-on IC with leadership responsibilities
