Power Optimization Engineer
Core
Develop chip power models, estimate power from microarchitecture, and devise power-saving techniques for AI ASICs.
Role type
Power Optimization Engineer (ASIC)
Builds
Model-specific AI chips (ASICs) optimized for power efficiency
Domain
Semiconductor hardware design / AI infrastructure
Deliverable
production ML models
Required skills
dynamic voltage and frequency scaling (DVFS), power-aware synthesis, glitch power reduction, efficient power delivery network implementation, gate-level power analysis (VCD/FSDB), low power design concepts, energy consumption estimation, data movement optimization
Preferred skills
RTL and layout level power optimization, PrimePower tool usage, clock power reduction, clock gating, clock gating techniques
Technologies
PrimePower, VCD, FSDB
Responsibilities
Develop chip power models from architecture; estimate chip power from microarchitecture; analyze power consumption at full-chip and unit levels; correlate estimated vs measured power; implement design for optimal power with cross-functional teams
Seniority
Mid-level, hands-on IC
