Senior Digital/AMS Validation and Integration Engineer
Core
Design and integrate RTL for control loops, calibration engines, and high-speed data paths in 10G+ Automotive SerDes transceivers, bridging digital logic with analog front-ends.
Role type
Senior Digital/AMS Design Engineer
Builds
Automotive SerDes transceivers (10G+)
Domain
Automotive semiconductor / High-speed mixed-signal interfaces
Deliverable
production ML models | product features
Required skills
SystemVerilog/Verilog, Static Timing Analysis (STA), Clock Domain Crossing (CDC), Python scripting, Logic analyzer usage, JTAG/I2C/SPI protocols
Preferred skills
10GBase-T/ASA/Automotive Ethernet standards, Analog Front End (AFE) hand-off, DFT/BIST insertion, Verilog-A modeling
Technologies
SystemVerilog, Verilog, Python, Perl, SDC
Responsibilities
Develop and integrate RTL for control loops and high-speed data paths; Define digital interfaces for analog blocks (ADCs, PLLs); Lead digital implementation flow and timing closure; Partner with validation team to bring up silicon and debug state machines; Execute block-level and chip-level simulations for PVT variations.
Seniority
Senior, hands-on IC
