Staff Digital Design Engineer
Core
Architecting and implementing digital FSM-based controllers and digital-on-top subsystems for mixed-signal and power management solutions.
Role type
Staff Digital Design Engineer (IC)
Builds
Digital controllers and subsystem IP for the onsemi Treo™ platform
Domain
Semiconductor / Mixed-signal and power management ICs
Deliverable
production ML models | product features | infrastructure
Required skills
Digital RTL design (SystemVerilog/Verilog), FSM-based control logic, Clock-domain crossing (CDC), Reset strategies, Low-power techniques, Timing constraints, Digital verification (simulation), Synthesis and STA
Preferred skills
Reusable IP delivery, UVM-based verification, Mixed-signal IC experience, UPF/CPF standards, AI/ML tools for design
Technologies
SystemVerilog, Verilog, UVM, UPF, CPF
Responsibilities
Design and implement digital FSM-based controllers; Develop clean, maintainable RTL suitable for reuse; Collaborate with analog and verification teams; Contribute to digital verification activities including testbench development and debug; Support digital back-end flows including synthesis and timing closure; Mentor junior engineers
Seniority
Staff, hands-on IC with mentorship