Lead Design Engineer - Physical Design
Core
Lead physical design implementation for high-speed digital DDR and HBM IP products targeting advanced process nodes (TSMC 3nm/5nm/7nm/12nm, Samsung 4nm/5nm/7nm/8nm/10nm) up to 6400MHz.
Role type
Senior IC physical design engineer (high-speed digital IP)
Builds
High-performance digital IP blocks (DDR, HBM) for semiconductor manufacturing
Domain
Semiconductor / IC Physical Design / Advanced Process Nodes
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Floorplan, Clock Tree Synthesis (CTS), Static Timing Analysis (STA), Physical verification, Power analysis, Scripting (Perl, C shell, TCL, Makefile, Python), EDA tools (Innovus, ICC, Calibre, Tempus, PrimeTime)
Preferred skills
Advanced design methodology for cutting-edge process nodes, PPA optimization
Technologies
Innovus, ICC, Calibre, Tempus, PrimeTime, TSMC 3nm/5nm/7nm/12nm, Samsung 4nm/5nm/7nm/8nm/10nm
Responsibilities
Develop scripts and tools to enhance physical design flow; Complete project tasks for high-speed digital IP; Solve design issues and establish flows to prevent recurrence; Analyze and summarize PPA optimization methodologies and implement optimal design parameters.
Seniority
Senior, hands-on IC