Principal Design Engineer
Core
Lead physical design implementation projects for low power and high speed ASICs at deep sub-micron nodes, including floor planning, P&R, timing closure, and signoff.
Role type
Principal Design Engineer (Physical Design)
Builds
ASIC chips for customers requiring high performance and low power
Domain
Semiconductor / VLSI Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> physical/clinical work (Note: This is a physical design role, not clinical. Correcting to: physical/clinical work is incorrect. The deliverable is physical chips. Let's map to the closest option or describe. The options are fixed. 'physical/clinical work' is the only one fitting 'physical' design in a literal sense, but it's a bad fit. However, the instruction says 'one of: ...'. I will select 'physical/clinical work' as it contains 'physical' but this is a semantic mismatch. Wait, the options are: production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work. None fit 'ASIC chips'. I must choose the best fit or omit? The instruction says 'one of'. I will choose 'product features' as the chip is a product feature, or 'infrastructure'. Actually, 'physical/clinical work' is likely a placeholder for 'physical work'. I will use 'product features' as the chip is a product. No, let's look at the options again. 'physical/clinical work' is the only one with 'physical'. I will use it despite the 'clinical' part being irrelevant, as it's the only option containing the word 'physical'. Alternatively, 'infrastructure' if we consider the flow. Let's go with 'product features' as the chip is a product. Actually, the most accurate description of the output is a physical chip. I will use 'product features' as it's the standard product output.
Required skills
hierarchical physical design strategies, deep sub-micron technology issues, low power design, DFT, static timing analysis, data skew balancing, duty cycle adjustment, EM/IR-drop/crosstalk analysis, formal verification, physical verification, DFM, P&R
Preferred skills
next generation physical design methodology development, leading flow development
Technologies
Cadence tools, ASIC design flow, DRC/LVS/Antenna, EM/IR signoff
Responsibilities
Perform physical design implementation (floor planning, place and route, clock tree synthesis, timing closure), execute power/signal integrity signoff, conduct physical verification (DRC/LVS/Antenna), lead next generation physical design methodology and flow development, collaborate with RTL design team for tapeouts
Seniority
Principal, hands-on IC