<Data Center>Serdes Digital IC Design Engineer
Core
Design and deliver ASIC Serdes PHY architecture for data center and AI products, focusing on low power, cost-effective, and high-speed performance.
Role type
Digital IC Design Engineer (Serdes PHY)
Builds
ASIC products for data center and AI applications
Domain
Semiconductor design, high-speed digital communication, analog macro design
Deliverable
production ML models | product features
Required skills
Serdes PHY architecture design, digital communication design (EQ, FIR), analog macro design (PLL, ADC/DAC, Calibration), SoC design (micro controller, bus protocol), ASIC design
Responsibilities
Design Serdes high-speed connection PHY architecture, contribute to low power and high-speed performance optimization, collaborate with international colleagues
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