interconnect fabric design and system level cache IP engineer
Core
Design interconnect, fabric, and system-level cache IP for products including smartphones and automotive.
Role type
Interconnect and System-Level Cache IP Engineer
Builds
Interconnect IP, Fabric IP, System-level cache IP
Domain
Semiconductor / SoC Design
Required skills
RTL design, Interconnect/Fabric IP design, System-level cache design, DV collaboration, Performance validation (Bandwidth/Latency), Design Quality Control (lint, CDC, DFT, UPF), RTL Front-End flow execution
Responsibilities
Design interconnect/fabric/cache IP for various products, Collaborate with DV team to ensure functionality, Work with performance validation team to meet BW/latency requirements, Execute IP Design Quality Control flows, Execute RTL Front-End flows
Seniority
Individual Contributor
